The present invention relates to a pulse width modulation inverter for varying speed of an AC-motor, and more particularly to a three-phase pulse width modulation waveform generator to be used for an inverter which uses a high speed switching such as a compound semiconductor bipolar transistor.
A triangle pulse wave modulation method is one of methods for generating a pulse width modulation signal. FIG. 1 is a diagram illustrative of waveforms of sign waves (U, V, W) and triangle wave for explaining a triangle pulse wave modulation method. The sign waves (U, V, W) are modulated with the triangle wave 401.
The three-phase pulse width modulation waveform generator comprises a first pulse width modulation waveform generator circuit for generating +U-phase and xe2x88x92U-phase pulse width modulation waveforms, a second pulse width modulation waveform generator circuit for generating +V-phase and xe2x88x92V-phase pulse width modulation waveforms, and a third pulse width modulation waveform generator circuit for generating +W-phase and xe2x88x92W-phase pulse width modulation waveforms. FIG. 2A is a circuit diagram illustrative of a circuit configuration of a first pulse width modulation waveform generator circuit for generating +U-phase and xe2x88x92U-phase pulse width modulation waveforms in a conventional three-phase pulse width modulation waveform generator. The first pulse width modulation waveform generator circuit of the three-phase pulse width modulation waveform generator has the following circuit elements. An up-down counter 1 which receives a count clock 2 is provided for performing up-count and down-count. A count register 3 is connected to the up-down counter 1 for storing a switching value and sending the switching value to the up-down counter 1 so that the up-down counter 1 switches from the up-count to the down-count in accordance with the switching value. A first buffer register 4 is connected to the count register 3. The first buffer register 4 receives a first transfer enabling signal 5 and transfer data to the counter resistor 3 in accordance with the first transfer enabling signal 5. A comparator 6 is connected to the up-down counter 1. A comparative register 7 is connected to the comparator 6. The comparative register 7 stores data for generating a U-phase pulse width modulation signal. A second buffer register 8 receiving a second transfer enabling signal 9 is connected to the comparative register 7 for transferring stored data to the comparative register 7 in accordance with the second transfer enabling signal 9. A delay circuit 10 is connected to the comparator 6 for generating a dead time which prevents formation of a short circuit. A waveform generator 14 is connected to the up-down counter 1 for receiving one of count direction signals 11 which indicate the up-count and the down-count from the up-down counter 1. The waveform generator 14 is also connected to the comparator 6 for receiving a correspondence-detected signal 12 from the comparator 6. The waveform generator 14 is also connected to the delay circuit 10 for receiving a delay signal from the delay circuit 10. The waveform generator 14 generates an +U-phase pulse width modulation signal 15 and a xe2x88x92U-phase pulse width modulation signal 16. A first three-state buffer 17 is provided which has an input terminal connected to the waveform generator 14 for receiving the +U-phase pulse width modulation signal 15 from the waveform generator 14. The first three-state buffer 17 receives an output stop signal 19, so that the first three-state buffer 17 stops the output of the +U-phase pulse width modulation signal 15. A second three-state buffer 18 is provided which has an input terminal connected to the waveform generator 14 for receiving the xe2x88x92U-phase pulse width modulation signal 16 from the waveform generator 14. The second three-state buffer 18 receives the output stop signal 19, so that the second three-state buffer 18 stops the output of the xe2x88x92U-phase pulse width modulation signal 16.
FIG. 2B is a circuit diagram illustrative of a circuit configuration of a second pulse width modulation waveform generator circuit for generating +V-phase and xe2x88x92V-phase pulse width modulation waveforms in the conventional three-phase pulse width modulation waveform generator. The second pulse width modulation waveform generator circuit of the three-phase pulse width modulation waveform generator has the same circuit elements as the first pulse width modulation waveform generator circuit. Namely, an up-down counter 1 which receives a count clock 2 is provided for performing up-count and down-count. A count register 3 is connected to the up-down counter 1 for storing a switching value and sending the switching value to the up-down counter 1 so that the up-down counter 1 switches from the up-count to the down-count in accordance with the switching value. A first buffer register 4 is connected to the count register 3. The first buffer register 4 receives a first transfer enabling signal 5 and transfer data to the counter resistor 3 in accordance with the first transfer enabling signal 5. A comparator 6 is connected to the up-down counter 1. A comparative register 7 is connected to the comparator 6. The comparative register 7 stores data for generating a V-phase pulse width modulation signal. A second buffer register 8 receiving a second transfer enabling signal 9 is connected to the comparative register 7 for transferring stored data to the comparative register 7 in accordance with the second transfer enabling signal 9. A delay circuit 10 is connected to the comparator 6 for generating a dead time which prevents formation of a short circuit. A waveform generator 14 is connected to the up-down counter 1 for receiving one of count direction signals 11 which indicate the up-count and the down-count from the up-down counter 1. The waveform generator 14 is also connected to the comparator 6 for receiving a correspondence-detected signal 12 from the comparator 6. The waveform generator 14 is also connected to the delay circuit 10 for receiving a delay signal from the delay circuit 10. The waveform generator 14 generates an +V-phase pulse width modulation signal 15 and a xe2x88x92V-phase pulse width modulation signal 16. A first three-state buffer 17 is provided which has an input terminal connected to the waveform generator 14 for receiving the +V-phase pulse width modulation signal 15 from the waveform generator 14. The first three-state buffer 17 receives an output stop signal 19, so that the first three-state buffer 17 stops the output of the +V-phase pulse width modulation signal 15. A second three-state buffer 18 is provided which has an input terminal connected to the waveform generator 14 for receiving the xe2x88x92V-phase pulse width modulation signal 16 from the waveform generator 14. The second three-state buffer 18 receives the output stop signal 19, so that the second three-state buffer 18 stops the output of the xe2x88x92V-phase pulse width modulation signal 16.
FIG. 2C is a circuit diagram illustrative of a circuit configuration of a third pulse width modulation waveform generator circuit for generating +W-phase and xe2x88x92W-phase pulse width modulation waveforms in the conventional three-phase pulse width modulation waveform generator. The third pulse width modulation waveform generator circuit of the three-phase pulse width modulation waveform generator has the same circuit elements as the first pulse width modulation waveform generator circuit. Namely, an up-down counter 1 which receives a count clock 2 is provided for performing up-count and down-count. A count register 3 is connected to the up-down counter 1 for storing a switching value and sending the switching value to the up-down counter 1 so that the up-down counter 1 switches from the up-count to the down-count in accordance with the switching value. A first buffer register 4 is connected to the count register 3. The first buffer register 4 receives a first transfer enabling signal 5 and transfer data to the counter resistor 3 in accordance with the first transfer enabling signal 5. A comparator 6 is connected to the up-down counter 1. A comparative register 7 is connected to the comparator 6. The comparative register 7 stores data for generating a W-phase pulse width modulation signal. A second buffer register 8 receiving a second transfer enabling signal 9 is connected to the comparative register 7 for transferring stored data to the comparative register 7 in accordance with the second transfer enabling signal 9. A delay circuit 10 is connected to the comparator 6 for generating a dead time which prevents formation of a short circuit. A waveform generator 14 is connected to the up-down counter 1 for receiving one of count direction signals 11 which indicate the up-count and the down-count from the up-down counter 1. The waveform generator 14 is also connected to the comparator 6 for receiving a correspondence-detected signal 12 from the comparator 6. The waveform generator 14 is also connected to the delay circuit 10 for receiving a delay signal from the delay circuit 10. The waveform generator 14 generates an +W-phase pulse width modulation signal 15 and a xe2x88x92W-phase pulse width modulation signal 16. A first three-state buffer 17 is provided which has an input terminal connected to the waveform generator 14 for receiving the +W-phase pulse width modulation signal 15 from the waveform generator 14. The first three-state buffer 17 receives an output stop signal 19, so that the first three-state buffer 17 stops the output of the +W-phase pulse width modulation signal 15. A second three-state buffer 18 is provided which has an input terminal connected to the waveform generator 14 for receiving the xe2x88x92W-phase pulse width modulation signal 16 from the waveform generator 14. The second three-state buffer 18 receives the output stop signal 19, so that the second three-state buffer 18 stops the output of the xe2x88x92W-phase pulse width modulation signal 16.
As described above, the first, second and third pulse width modulation waveform generator circuits of the three-phase pulse width modulation waveform generator have the same circuit configuration as each other, provided that the up-down counter 1, the count resistor 3 and the buffer resistor 4 are commonly provided to the first, second and third pulse width modulation waveform generator circuits, for which reason processes for generating the pulse width modulation signals will be described by taking the first pulse width modulation waveform generator circuit as one example. FIG. 3 is a diagram illustrative of waveforms of signals to explain operations of generating +W-phase and xe2x88x92W-phase pulse width modulation waveforms in the first pulse width modulation waveform generator circuit of FIG. 2A of the three-phase pulse width modulation waveform generator.
The first buffer register 4 allows a central processing unit not illustrated to re-write or re-set data to be stored therein. Upon receipt of the first transfer enable signal 5, the first buffer register 4 transfers the data to the count register 3. The second buffer register 8 also allows a central processing unit not illustrated to re-write or re-set data to be stored therein. Upon receipt of the second transfer enable signal 9, the second buffer register 8 transfers the data to the comparative register 7. A 0-detected signal of the up-down counter 1 is used as the transfer enable signal.
The up-down counter 1 operates in accordance with the count clock 2 externally supplied. If an up-counted value of the up-down counter 1 is made correspond to the value supplied from the count register 3 during the up-count operation of the up-down counter 1, then the up-counter 1 stops the up-count operation and in place starts the down-count. Namely, upon correspondence between the up-counted value of the up-down counter 1 and the value supplied from the count register 3, the up-down counter 1 switches the up-count operation to the down-count operation. If a down-counted value becomes 0 during the down-count operation of the up-down counter 1, the up-down counter 1 stops the down-count operation and in place starts the up-count. Namely, if the down-counted value becomes 0, then the up-down counter 1 switches the down-count operation to the up-count operation.
The comparator 6 receives the counted value from the up-down counter 1 and also receives the U-phase pulse width modulation signal generation data from the comparative register 7 for comparing the counted value with the U-phase pulse width modulation signal generation data. If the counted value corresponds to the U-phase pulse width modulation signal generation data, then the comparator 6 generates the correspondence-detected signal 12 which is transmitted to both the delay circuit 10 and the waveform generator 14. The delay circuit 10 receives the correspondence-detected signal 12 from the comparator 6 for generating the delay signal 13 which indicates the dead-time for preventing the short circuit formation. The waveform generator 14 receives the count direction signal 11 from the up-down counter 1 and also receives the correspondence-detected signal 12 from the comparator 6 as well as receives the delay signal 13 from the delay circuit 10, so that the waveform generator 14 generates the +U-phase pulse width modulation signal 15 and the xe2x88x92U-phase pulse width modulation signal 16. The first three-state buffer 17 receives the +U-phase pulse width modulation signal 15 from the waveform generator 14. The first three-state buffer 17 also receives the output stop signal 19, so that the first three-state buffer 17 stops the output of the +U-phase pulse width modulation signal 15 upon receipt of the output stop signal 19. The second three-state buffer 18 receives the xe2x88x92U-phase pulse width modulation signal 16 from the waveform generator 14. The second three-state buffer 18 also receives the output stop signal 19, so that the second three-state buffer 18 stops the output of the xe2x88x92U-phase pulse width modulation signal 16 upon receipt of the output stop signal 19.
FIG. 4 is a flow chart illustrative of a pulse width modulation output process by a central processing unit. The pulse width modulation output process is made as follows. In the first step S31, it is verified that the frequency change is required. If required, in the second step S32, the frequency is changed, before in the third step S33, the timing is set. If not required, in the third step S33, the timing-setting process is carried out as shown in FIG. 5.
FIG. 5 is a flow chart illustrative of a timing-setting process by a central processing unit. The timing-setting process is carried out as follows. In a first step S20, a sine wave table is referred to obtain data, wherein an address to be referred is calculated on the basis of a step address which has been previously set in accordance with the output frequency thereby obtaining the sine wave data. In a second step S21, a product of the V/f modulation rate is calculated to obtain timing data, wherein the V/f modulation rate has previously been set. In a third step S22, an off-set correction is made on the basis of the off-set correction value which has previously been set. In a fourth step S23, a timing is set by setting the timing data to the buffer registers of the first, second and third pulse width modulation waveform generator circuits of the three-phase pulse width modulation waveform generator.
FIG. 6 is a flow chart illustrative of an output frequency change process by a central processing unit. In a first step S24, a step address is set. In a second step S25, the V/f modulation rate is set. In a third step S26, an off-set correction value is set.
The first pulse width modulation waveform generator circuit for generating +U-phase and xe2x88x92U-phase pulse width modulation waveforms in the conventional three-phase pulse width modulation waveform generator need to set the buffer registers with the carrier cycle data which correspond to the A, B and C in FIG. 3 to be used in this carrier cycle and also with comparative data which correspond to D, E, and F in FIG. 3, until the start of each carrier cycle, for which reason the central processing unit prepares data to be written to the buffer register in accordance with the expected pulse width modulation waveform for every carrier cycles.
The second pulse width modulation waveform generator circuit for generating +V-phase and xe2x88x92V-phase pulse width modulation waveforms in the conventional three-phase pulse width modulation waveform generator need to set the buffer registers with the carrier cycle data to be used in this carrier cycle and also with comparative data, until the start of each carrier cycle, for which reason the central processing unit prepares data to be written to the buffer register in accordance with the expected pulse width modulation waveform for every carrier cycles.
The third pulse width modulation waveform generator circuit for generating +W-phase and xe2x88x92W-phase pulse width modulation waveforms in the conventional three-phase pulse width modulation waveform generator need to set the buffer registers with the carrier cycle data to be used in this carrier cycle and also with comparative data, until the start of each carrier cycle, for which reason the central processing unit prepares data to be written to the buffer register in accordance with the expected pulse width modulation waveform for every carrier cycles.
The values to be set are calculated by operations of the central processing unit. The central processing unit performs operations in correspondence with the expected output frequency on the basis of the basic sine wave data table which has already been prepared in the memory.
The central processing unit operate the setting data corresponding to the U-phase, the V-phase and the W-phase for every carrier cycles so as to write the setting data into the buffer register of each of the first, second and third pulse width modulation waveform generator circuits for generating +U-phase and xe2x88x92U-phase pulse width modulation waveforms, +V-phase and xe2x88x92V-phase pulse width modulation waveforms, and +W-phase and xe2x88x92W-phase pulse width modulation waveforms in the conventional three-phase pulse width modulation waveform generator. In order to change the output frequency, it is necessary to set parameters to be used in the operations of the central processing unit in accordance with the output frequency in addition to the above processes. This means that the load to the throughput of the central processing unit is large.
Further, it is necessary that the parameters, for example, the step address, the V/f modulation rate, and the off-set correction value, to be used in the timing setting process have previously be calculated in accordance with the output frequency. It is necessary for changing the output frequency to perform both the frequency change process and the timing setting process. This means that the load to the throughput of the central processing unit is large.
In the above circumstances, it had been required to develop a novel three-phase pulse width modulation waveform generator free from the above problem.
Accordingly, it is an object of the present invention to provide a novel three-phase pulse width modulation waveform generator free from the above problems.
It is a further object of the present invention to provide a novel three-phase pulse width modulation waveform generator which is capable of reducing the load to the central processing unit in generating the three-phase pulse width modulation waveforms.
It is a still further object of the present invention to provide a novel three-phase pulse width modulation waveform generator which is capable of reducing the load to the central processing unit in the process for changing the output frequency in order to generate the three-phase pulse width modulation waveforms.
It is yet a further object of the present invention to provide a novel three-phase pulse width modulation waveform generator which is capable of changing carrier cycles by switching count cycles of an up-down counter, which serve as a base for the carrier frequency, wherein the switch is made without discontinuation of the counting operation of the up-down counter.
It is a further more object of the present invention to provide a novel three-phase pulse width modulation waveform generator which allows that a sine wave data group on a sine wave table has been referred prior to changing the carrier cycle, before this sine wave data group is utilized as another sine wave data group for a different output frequency, whereby it is unnecessary to calculate a table address in correspondence with the output frequency in referring the sine wave table.
It is more over object of the present invention to provide a novel three-phase pulse width modulation waveform generator which allows that a sine wave data group on a sine wave table has been referred prior to changing the carrier cycle, before this sine wave data group is utilized as another sine wave data group for a different output frequency, whereby it is unnecessary to calculate a step address to be used for operation for the table address.
The first present invention provides a three-phase pulse width modulation waveform generator having at least an up-down counting circuitry which comprises: an up-down counter for performing an up-count or a down-count upon an external input of a count clock signal; and a count controller having an output side connected to an input side of the up-down counter for sending the input side of the up-down counter a count enable signal which enables the up-down counter to perform the up-count or the down-count.
The above and other objects, features and advantages of the present invention will be apparent from the following descriptions.